SureCore has announced its new in-memory computing technology called CompuRAM. This will make edge computing solutions more energy efficient. Currently, sensor data often must be sent from iot devices to servers for processing, creating connection requirements and inevitable delays. This is not satisfactory for time-pressed applications and requires more computations inside the device, with AI processing at the edge. Power is an important design constraint in iot devices, so any additional calculations associated with AI must be done in an energy-efficient manner. The company's existing low-power memory solution already provides a way to add large amounts of additional memory needed for AI applications without dramatically increasing power demand. In-memory computing further saves power by reducing the need to move large amounts of data around the chip, since the initial processing of the data takes place very close to the storage array itself.
Tony Stansfield, CTO of SureCore, explains: "Our deep knowledge of memory technology means that we have been able to create a solution for the next technical requirement of integrating arithmetic operations in memory. This is another example of us seeing what the industry needs in the near future and developing a solution that will be ready when the need for edge AI becomes mainstream. Reducing power consumption is what we do, as we have demonstrated with existing technologies such as our EverOn and PowerMiser SRAM families, which achieve near-threshold operation and 50% dynamic power outages, respectively. Our solutions are all designed to create products for the next generation of ultra-low power applications that would not exist without their energy saving technologies."
While on-chip memory is better, faster, and more energy efficient than transferring data back and forth between off-chip memory, integrating memory and computing power offers significant energy saving advantages. Its in-memory computing technology enables this integration by embedding computing power in storage arrays in an approach that is compatible with existing silicon-proven low-power storage designs.
