In office buildings, factory floors and cars, software is replacing mechanical parts and fixed circuits. For example, after using a smart lock to replace a mechanical lock, the user can control the smart lock through a mobile phone application, while the manufacturer can update, improve or correct the function of the smart lock through software. Under this trend, people's requirements for memory are constantly increasing, and this challenge cannot be ignored.
In microcontrollers (MCUS), which are often embedded with flash memory, the capacity of memory is also increasing rapidly. In addition to macro trends, some specific developments in MCUS, including higher compute bandwidth, functional integration, and the inclusion of additional large communication stacks, also dictate the need for greater capacity flash memory. When the need for over-the-air updates arises, these needs naturally double as both the original image and the backup image need to be stored.Faced with the pressure of increasing memory capacity, many designers develop "memory anxiety" : the fear that there will not be enough memory on chip. And the rapid growth in demand for memory is unsustainable, both in terms of scalability and cost.
One way to solve the above problems is to use an external flash MCU solution.
Separating the MCU from flash technology creates a more scalable and cost-effective system. In terms of scalability, embedded flash MCUS need to switch to a completely different device to upgrade to a larger capacity memory. On the cost side, as performance requirements increase and the number of process nodes manufactured by the MCU decreases, flash memory simply cannot reduce the number of process nodes as typical digital complementary metal oxide semiconductor (CMOS) processes do due to the fact that flash memory has emulators such as charge pumps.
Because it is difficult to reduce process nodes, embedded flash MCUS incur additional costs, especially when the memory capacity is large. However, removing flash memory from the MCU also presents design challenges, especially in terms of performance, information security and functional safety. To design external flash memory to realize cost savings and scalability benefits and overcome engineering challenges, Texas Instruments (TI) developed OptiFlash memory technology. Figure 1 shows a schematic diagram of the OptiFlash technology architecture on the TI AM263P4-Q1 MCU.
Figure 1: Demonstration of OptiFlash memory technology on an AM263P4-Q1 MCU
What is OptiFlash technology?
OptiFlash technology is a combination of hardware memory controller accelerators and software tools. To address the performance challenge, the AM263P4-Q1 MCU uses a high-bandwidth, low-pin, eight-channel serial peripheral interface for external flash integrated circuits. The interface has eight data channels, can run at up to 133MHz double data rate, and also adds a flash memory cache as a flash instruction controller, placing the cached instructions in the on-chip RAM. Flash caching alone can increase in-place execution (XIP) performance by up to 80%, depending on code structure.
Another common performance challenge with external flash memory is response time. With hardware accelerators, OptiFlash technology can process multiple parts of the response process in parallel, enabling initial controller LAN messages to reach as fast as 56ms or 118ms (until fully operational). It depends on the image size. In addition to hardware accelerators, OptiFlash technology includes static code analysis tools such as Intelligent Allocation tools (which analyze application code and recommend code allocation in tightly coupled memory, RAM, or flash memory, depending on the frequency of execution).
To help achieve the full level of cybersecurity of up to ASIL D's Automotive Security Integrity Level (ASIL) and Up to Electronic Secure Vehicle Intrusion Protection Application (EVITA) Hardware Security Module (HSM), When OptiFlash technology is used in devices, functional safety and information security should be considered when external flash memory is enabled. To ensure the integrity of data transmission, Texas Instruments implemented inline error correction codes in the hardware to detect and correct transmission errors.
On the security side, due to the use of external flash memory, in theory, the attacker will probe the data line and read the code being executed through a man-in-the-middle attack method. In general, because any data that is "listened to" on the data line is encrypted, encrypting the code and data on an external flash drive reduces this possibility. But because we execute in place via flash memory, OptiFlash includes a dynamic authentication and encryption block that allows security functions to be performed in hardware without any user action.
When these performance accelerators are combined with large-capacity on-chip RAM (3.5MB in AM263P4-Q1), overall performance can be performed almost directly from on-chip RAM. Texas Instruments benchmark data shows that with TI OptiFlash technology, XIP performance degrades by up to 10 percent fewer CPU cycles compared to on-chip RAM execution.
Conclusion
With the increasing demand for memory in software-defined architectures, OptiFlash memory technology shifts the memory architecture paradigm to enable the scalability and cost-effectiveness of external flash memory. This will help more systems achieve rich functionality. For example, critical software updates to cars via over-the-air updates, or networking to make systems that require more space for larger communication stacks more connected. By enabling more scalable and cost-effective memory storage, OptiFlash memory technology can clear the road to many emerging trends in the automotive industry.
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