Texas Instruments LMK61E2 ultra-low jitter, fully programmable PLLatinum oscillator with fractional-N frequency synthesizer.
The device includes an integrated VCO to generate commonly used reference clocks. The output can be configured as LVPECL or LVDS or HCSL. The device has a self-starting function of an on-chip EEPROM that has been factory programmed to generate 156.25MHz LVPECL output. Device registers and EEPROM settings can be fully programmed in the system via the I2C serial interface.
Internal power regulation provides excellent power ripple rejection (PSRR), reducing the cost and complexity of power transmission networks. The device provides fine and coarse frequency margin options through the I2C serial interface to support system design verification tests (DVT), such as standard compliance and system timing margin tests.
